The present invention relates to the electrical and electronic arts, and more specifically, to semiconductor fabrication techniques and the like.
Metal-oxide-semiconductor field-effect transistors (MOSFETs) have a source, a drain, and a metal oxide gate electrode. The metal gate is electrically insulated from the main semiconductor n-channel or p-channel by a thin layer of insulating material; for example, silicon dioxide or a high dielectric constant (high-k) dielectric. This makes the input resistance of the MOSFET relatively high. The gate-to-source voltage controls whether the transistor is ON or OFF.
N-type field effect transistors (NFETs) and p-type field effect transistors (PFETs) are two types of complementary MOSFETs. The NFET uses electrons as the current carriers and has n-doped source and drain regions. The PFET uses holes as the current carriers and has p-doped source and drain regions.
The FinFET is a type of MOSFET. The FinFET is a multiple-gate MOSFET device that mitigates the effects of short channels and reduces drain-induced barrier lowering. The “fin” refers to a semiconductor material patterned on a substrate that often has three exposed surfaces that form the narrow channel between the source and drain regions. A thin dielectric layer arranged over the fin separates the fin channel from the gate. Since the fin provides a three-dimensional surface for the channel region, a larger channel length may be achieved in a given region of the substrate as opposed to a planar FET device.
FinFETs can be fabricated with either a ‘gate-first’ or a ‘gate-last’ process. In a gate-last sequence, a dummy polysilicon gate is initially patterned and used for source and drain formation; then the dummy gate is removed and the replacement metal gate composition is patterned.
Referring to the Transmission electron microscopy (TEM) image in FIG. 1, in current FinFET fabrication, a bowl-shaped profile for the gate trench is observed, impacting the device performance and/or yield. In particular, different spacer thickness (THK) along the bowl shape impacts the gate (e.g. polysilicon conductor (PC)) profile and/or the effective capacitance, Ceff, of the circuit). The issues with the bowl-shaped profiles may arise in both dummy gate/gate last and gate first fabrication techniques. This bowl shape is a consequence of, e.g., Flowable Chemical Vapor Deposition (FCVD) plus anneal, which results in pulling of Polycrystalline silicon (Poly) at two sides. The “pulling” is the result of tensile stress induced by the vapor deposition and annealing. In FIG. 1 (which depicts a prior art or point-of-reference (POR) example), element 103 is the substrate with fins; and elements 105 represent SiO2 dielectric defining trenches 107 into which the actual gates will subsequently be deposited. The dotted lines 101 show the bowl-shaped profile of the trenches. The demo gate length achieves target PC CD (critical dimension) at the fin surface, target PC CD+3 nm at the widest point, and target PC CD-4 nm at the top. The thinness of the gate at the upper part of the bowl shape can potentially cause gate metal gap filling problems, and the top part of the bowl shape could cause leakage problems from spacer reactive ion etching (RIE). The bowl-shaped variations in the trench width are undesirable. Exemplary dimensions herein are not to be taken as limiting unless recited in the claims.